Overview - Load and Store Multiple

The Load and Store Multiple addressing mode is divided into 4 submodes. Load instructions load subsets or even all the general purpose registers specified by reg from memory. Store instructions store subsets or even all the general purpose registers specified by reg to memory. Addresses produced by this addressing mode are sequential; hence registers specified by reg are loaded in ascending order from the lowest to the highest memory address. The general syntax of the addressing mode is provided in the following section.

General Syntax

LDM|STM [condition] addr_mode basereg[!], reg {,reg}

where:

condition	One of 16 conditions. See Condition Code Status.
basereg	Base register used by addr_mode .
!	Sets the W bit (21).
reg	Valid register(s) to be loaded.

addr_mode can be one of the following 4 submodes:

Submodes	Description
IA	Increment after. It forms a range of addresses for Load and Store Multiple instructions. See Load/Store Multiple: Increment After (AM 4).
IB	Increment before. It forms a range of addresses for Load and Store Multiple instructions. See Load/Store Multiple: Increment Before (AM 4).
DA	Decrement after. It forms a range of addresses for Load and Store Multiple instructions. See Load/Store Multiple: Decrement After (AM 4).
DB	Decrement before. It forms a range of addresses for Load and Store Multiple instructions. See Load/Store Multiple: Decrement Before (AM 4).

General Encoding

The following table illustrates the encoding for this addressing mode:

Encoding - Addressing Mode 4

31		28	27	26	25	24	23	22	21	20	19		16	15		0
condition			1	0	0	P	U	S	W	L	basereg			reglist

where:

Bit[24]	Is the P bit. See below.
Bit[23]	Is the U bit. U == 1 indicates that transfers are upwards from basereg . U == 0 indicates that transfers are downwards from basereg .
Bit[22]	Is the S bit. The S bit indicates that the CPSR is loaded from the SPSR for Load instructions that load the PC. In privileged mode it indicates that the User mode banked registers are transferred for Load instructions that do not load the PC and all Store instructions.
Bit[21]	Is the W bit. The W bit indicates that basereg is updated. U == 1 indicates that basereg is incremented by four times the number of registers in reglist . U == 0 indicates that basereg is decremented by four times the number of registers in reglist .
Bit[20]	Is the L bit. L == 1 indicates a Load instruction. L == 0 indicates a Store instruction.
Bits[15:0]	reglist has one bit dedicated to each register; bit[0] denotes R0 , bit[15] denotes R15 ( PC ). At least one bit must be set.

The meaning of the P bit (bit[24]) depends on the setting of the U bit:

	U==0	U==1
P==0	The address contained in basereg is one word beyond the top of the range.	The address contained in basereg is one word below the bottom of the range.
P==1	The address contained in basereg is accessed at the bottom of the range.	The address contained in basereg is accessed at the top (U == 1) of the range.

Alternative Names

The IA, IB, DA and DB addressing modes are most useful for block transfers, particularly when the Load and Store Multiple instructions have used the addressing mode, as the data is loaded in the same way as it was stored.
When Load and Store Multiple instructions are used to access the stack, different addressing modes are required as pop and push operations adjust the stack in opposite directions.
An alternative syntax is available for stack operations:

Stack	Syntax	Description
Empty Ascending	EA	Stack pointer points to the first unused location and grows towards increasing memory locations.
Full Ascending	FA	Stack pointer points to the last used location and grows towards increasing memory locations.
Empty Descending	ED	Stack pointer points to the first unused location and grows towards decreasing memory locations.
Full Descending	FD	Stack pointer points to the last used location and grows towards decreasing memory locations.

EA or FD stack types are recommended when defining stacks for coprocessors. Coprocessor data can be pushed or popped with a single STC or LDC instruction respectively to this type of stack. ED and FA coprocessor stack accesses require multi-instruction sequences.

Further Information

See Assembler Instructions